About PCB Impedance Control

Without impedance control, considerable signal reflections and signal distortions can result, leading to design failure. Common signals, such as the PCI bus, PCI-E bus, USB, Ethernet, DDR memory, and LVDS signals, need to be controlled for impedance. Impedance control ultimately needs to be implemented through PCB design, and higher requirements are placed on the PCB process. After communicating with the PCB factory and using the EDA software, the impedance of the traces is controlled according to the requirements of signal integrity.

Different routing methods can calculate the corresponding impedance value through calculation.

Microstrip line

It consists of a strip conductor and a ground plane with a dielectric in the middle. If the dielectric constant of the dielectric, the width of the line, and its distance from the ground plane are controllable, its characteristic impedance is also controllable, and its accuracy will be within ± 5%.


A stripline is a copper strip placed in the middle of a dielectric between two conductive planes. If the thickness and width of the line, the dielectric constant of the medium, and the distance between the two ground planes are all controllable, then the characteristic impedance of the line is also controllable and the accuracy is within 10%.

Structure of multilayer boards


In order to well control the impedance of the PCB, we must first understand the structure of the PCB:

Generally speaking, the multi-layer board is formed by laminating and pressing a core board and a prepreg layer on top of each other. The core board is a hard, specific thickness, two bread copper plate, which is the basic material of the printed board. . The prepreg forms a so-called wetting layer, which plays the role of bonding the core board. Although it has a certain initial thickness, its thickness will change during the pressing process.

Usually the two outermost dielectric layers of a multilayer board are infiltration layers, and a separate copper foil layer is used as the outer copper foil on the outside of the two layers. The original thickness specifications of the outer copper foil and the inner copper foil are generally 0.5OZ, 1OZ, 2OZ (1OZ is about 35um or 1.4mil), but after a series of surface treatments, the final thickness of the outer copper foil is generally Will increase by almost 1OZ. The inner layer of copper foil is the copper clad on both sides of the core plate, and the final thickness is slightly different from the original thickness, but it is generally reduced by several um due to etching.

The outermost layer of a multilayer board is a solder mask, which is what we often call "green oil". Of course, it can also be yellow or other colors. The thickness of the solder resist layer is generally not easy to determine accurately. The area without copper foil on the surface is slightly thicker than the area with copper foil, but because the thickness of the copper foil is missing, the copper foil still looks more prominent. When we use You can feel it when you touch the surface of the printed board with your fingers.

PCB parameters

The PCB parameters of different printed board factories will be slightly different. Through communication with the technical support of the circuit board factory, some parameter data of the factory are obtained:

Surface copper foil: There are three thicknesses of surface copper foil material that can be used: 12um, 18um, and 35um. The final thickness after processing is about 44um, 50um and 67um.

Introduction to tools for impedance calculation:

After we understand the structure of the multilayer board and the required parameters, we can use EDA software to calculate the impedance. You can use Allegro to calculate, but here I recommend another tool, Polar SI9000, which is a very good tool for calculating characteristic impedance. Many printed board manufacturers now use this software.

Whether it is a differential line or a single-ended line, when calculating the characteristic impedance of the inner layer signal, you will find that there is only a slight gap between the calculation results of Polar SI9000 and Allegro. This is related to some details such as the cross section shape. However, if you are calculating the characteristic impedance of the surface signal, I suggest you choose the Coated model instead of the Surface model, because this model takes into account the existence of the solder mask, so the results will be more accurate.

Since the thickness of the solder mask is not easy to control, you can also use an approximate method according to the board manufacturer's recommendation: subtract a specific value from the surface model calculation result, it is recommended to subtract 8 ohms for differential impedance, and single-ended impedance Go for 2 ohms.

PCB requirements for differential pair routing

(1) Determine the wiring mode, parameters and impedance calculation. Differential pair traces are divided into two modes: the outer microstrip line differential mode and the inner stripe line differential mode. By properly setting the parameters, the impedance can be calculated using related impedance calculation software (such as POLAR-SI9000) or the impedance calculation formula.

(2) Take parallel isometric lines. Determine the line width and spacing of the traces, and strictly follow the calculated line width and spacing when routing. The distance between the two lines must always remain the same, that is, they must remain parallel. There are two kinds of parallel ways: one is for two wires to go side-by-side, and the other is for two wires to go over-under. Generally avoid the use of the latter, that is, inter-layer differential signals, because in the actual processing of PCB boards, the accuracy of the lamination alignment between the laminations is much lower than the accuracy of the same layer etching, and the dielectric loss during the lamination process cannot be used Ensure that the distance between the differential lines is equal to the thickness of the interlayer dielectric, which will cause the differential impedance of the interlayer differential pair to change. It is recommended to use differences within the same layer whenever possible.