DDR particle surface bottom blind design highlights
1. The board space is small, and 4 DDR particles occupy a large space.
2. BGA side DDR signal level planning
3. The third-order blind buried DDR address control signal needs to be T.
[Our countermeasures]: 1. DDR desktop bottom sticker, third-order blind burying
2. The BGA device is divided into three lines, the outer circle is separated from the first layer of the device, the middle one is used with the second layer of the device, and the inner ring is the third layer of the device.
3. The DDR signal is on the PIN and the address control signal is used alternately.
The DDR layout takes up less space, all signals have a ground reference, and the DDR signal simulation quality is good.