High-speed circuit layout and wiring must be known
01 Power layout and wiring related
Many times the current required by digital circuits is not continuous, so there will be a surge current for some high-speed devices.
If the power supply circuitries are very long, the presence of inrush current will lead to high frequency noise, which will be introduced into other signals. And will inevitably exist in high speed circuit parasitic inductance and parasitic resistance and parasitic capacitance, so the high frequency noise will eventually coupled to other circuits, and as a result of the existence of parasitic inductance can also lead to walk line can withstand the waves surge current ability to drop, leading to a portion of the pressure drop, disability is likely to make the circuit.
So it is very important to add a bypass capacitor in front of the digital device. The larger the capacitance is, the more energy it can transmit is limited by the transmission rate, so it is common to combine a large capacitance with a small capacitance to meet the full frequency range.
Avoid hot spot generation: Signal through holes can generate VOIDS in the power layer and the underlying layer. Therefore, improper placement of the hole is likely to increase the current density in some areas of the power supply or ground plane. And these places where the current density increases are called hot spots.
Therefore, we should try our best to avoid this situation when setting through holes, so as not to cut the plane and eventually cause EMC problems.
Often the best way to avoid hot spots is to place through holes in a mesh pattern so that the current density is uniform and the plane is not isolated, so the backflow path is not too long and therefore does not cause EMC problems.
02 Bending mode of wiring
When laying the high-speed signal line, the signal line should avoid bending as far as possible. If you have to bend the line, do not use sharp or right angles. Instead, use obtuse angles.
In the layout of high-speed signal lines, we often through the serpentine line to achieve equal length, the same serpentine line is actually a bending of the line. Line width, spacing, and bending mode should be reasonably selected, spacing should meet the 4W/1.5W rule.
03 Signal proximity
If the distance between high-speed signal lines is too close, it is easy to produce crosstalk. Sometimes, due to layout, frame size and other reasons, the distance between high-speed signal lines exceeds our minimum required distance, so we have to increase the distance between high-speed signal lines near the bottleneck as much as possible.
In fact, if the space is enough to allow, try to increase the distance between the two high-speed signal lines.
04 line stubs
Long stub lines act as an antenna and can cause serious EMC problems if not handled properly.
At the same time, stub lines also cause reflection, reducing the integrity of the signal. Stub wires are most likely to be generated when pull-up or pull-down resistors are added to high speed signal lines, and stub wires can be used to process stub wires.
As a rule of thumb, this becomes a problem if the stub line is longer than 1/10 of a wavelength and can be used as an antenna.
05 Impedance discontinuity
The impedance value of a trace generally depends on its line width and the distance between the trace and the reference plane. The wider the wire, the smaller the impedance. And in some interface terminals also device pads, the same principle applies.
When the pad of an interface terminal is connected to a high-speed signal line, if the pad is very large and the high-speed signal line is very narrow, the large pad will have a small impedance, while the narrow wire must have a large impedance. In this case, there will be an impedance discontinuity, and the impedance discontinuity will produce signal reflection.
Therefore, in order to solve this problem, a copper sheet is placed under the large solder pad of the interface terminal or device, and the reference plane of the solder pad is placed in another layer, so as to increase the impedance and make the impedance continuous.
Perforations are another source of impedance discontinuity. To minimize this effect, unneeded copper sheeting in the inner layer and through connection should be removed.
This operation can actually be eliminated at the time of design through CAD tools or contact PCB manufacturers to eliminate the unwanted copper skin, to ensure the continuity of impedance.
06 Differential Signal
We must ensure equal width and equal spacing for high-speed differential signal lines to achieve specific differential impedance values. Therefore, the distribution of the differential signal line as far as possible to ensure symmetry.
Do not place holes or components in differential lines. Places of holes or components in differential lines will cause EMC problems and impedance discontinuities.
Sometimes, some high - speed differential signal lines require serial coupling capacitors. The coupling capacitor also needs to be arranged symmetrically. At the same time, the package of the coupling capacitor should not be too large. It is recommended to use 0402,0603 and it is also acceptable.
In general, through holes will cause a large impedance discontinuity, so for high-speed differential signal pairs, through holes should be minimized, and if through holes are to be used, they should be arranged symmetrically.
In some high-speed signal interfaces, such as bus, the arrival time and delay error between the signal lines should be considered. For example, in a set of high-speed parallel buses, the arrival time of all data signal lines must be guaranteed within a certain time delay error to ensure its establishment time and maintain time consistency. In order to satisfy this requirement, we have to consider the equilength.
However, the high-speed differential signal line must guarantee strict time delay for two signal lines, otherwise communication failure is very likely. Therefore, in order to meet this requirement, the serpentine line can be used to achieve equal length, and then the time delay requirements can be satisfied.
Serpentine lines should generally be placed at the source of the loss, not at the far end. Only at the source can the signals of the positive and negative ends of the difference line be transmitted synchronously most of the time.
Wiring bending is one of the sources of the loss of length. For the wiring bend, its realization equal length should be close to the bend (<=15mm).
If two wires are bent, and the distance between them is less than 15mm, the loss of length between them will compensate each other, so there is no need to do equal length processing.
For different parts of high-speed differential signal lines, they should be independent and equal in length. The through-hole, series-coupling capacitance, and interface terminal are two parts of the high-speed differential signal line, so special attention should be paid at this time.
Make sure they're equal lengths. Because a lot of EDA software in DRC are only concerned about whether the whole line is lost.
For interfaces such as LVDS display devices, there will be a number pair difference pair at the same time, and the timing sequence requirements between the difference pairs are usually very strict, and the time delay requirements are very small. Therefore, for such differential signals, we generally require compensation in the same plane. Because the signal speeds are different at different layers.
Some EDA software will calculate the wiring length within the length when calculating the wiring length. If the length compensation is carried out at this time, the actual result will lose the length. So pay special attention at this time, when using some EDA software.
Whenever possible, always choose a symmetrical outlet to avoid the need to end up with a serpentine route for equal length.
If space permits, try to add a small loop at the source of the short difference line to realize compensation, rather than through the serpentine line to compensate.