Impedance matching for high speed PCB design
Impedance matching means that when the energy is transmitted, the load impedance is required to be equal to the characteristic impedance of the transmission line, and the transmission at this time does not cause reflection, which indicates that all energy is absorbed by the load. On the contrary, there is energy loss in the transmission. In high-speed PCB design, the matching of impedance is related to the quality of the signal.
When do PCB traces need to be impedance matched?
Do not mainly look at the frequency, but the key is to look at the edge of the signal steeply, that is, the rise/fall time of the signal. It is generally considered that if the rise/fall time of the signal (in 10% to 90%) is less than 6 times the wire delay, it is high speed. Signals must pay attention to the problem of impedance matching. The wire delay is generally 150ps/inch.
During the propagation of the signal along the transmission line, if there is a uniform signal propagation speed throughout the transmission line and the capacitance per unit length is the same, then the signal always sees a completely uniform instantaneous impedance during propagation. Since the impedance remains constant throughout the transmission line, we give a specific name to indicate this characteristic or characteristic of a particular transmission line, which is called the characteristic impedance of the transmission line. Characteristic impedance is the value of the instantaneous impedance seen by the signal as it propagates along the transmission line. The characteristic impedance is related to the board layer where the PCB wire is located, the material used for the PCB (dielectric constant), the width of the trace, and the distance between the wire and the plane, regardless of the length of the trace. The characteristic impedance can be calculated using software. In high-speed PCB layout, the trace impedance of a digital signal is generally designed to be 50 ohms, which is an approximate number. The coaxial cable baseband is generally specified to be 50 ohms, with a frequency band of 75 ohms and a twisted pair (differential) of 100 ohms.
Common impedance matching method
1, tandem terminal matching
Under the condition that the signal source impedance is lower than the characteristic impedance of the transmission line, a resistor R is connected in series between the source end of the signal and the transmission line, so that the output impedance of the source end matches the characteristic impedance of the transmission line, and the signal reflected from the load end is suppressed. A re-reflection occurred.
Matching resistor selection principle: The sum of the matching resistor value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. Common CMOS and TTL drivers, whose output impedance varies with the level of the signal. Therefore, for TTL or CMOS circuits, it is impossible to have a very correct matching resistor, which can only be compromised. The signal network of the chain topology is not suitable for series termination matching, and all loads must be connected to the end of the transmission line.
Series matching is the most common method of terminal matching. It has the advantage of low power consumption, no additional DC load on the driver, no additional impedance between the signal and ground, and only one resistor component. Common applications: impedance matching of general CMOS and TTL circuits. The USB signal is also sampled by this method for impedance matching.
2, parallel terminal matching
In the case where the impedance of the signal source is small, the input impedance of the load terminal is matched with the characteristic impedance of the transmission line by increasing the parallel resistance, so as to eliminate the reflection at the load end. The implementation form is divided into two types: single resistance and double resistance.
Matching resistance selection principle: In the case of a high input impedance of the chip, for a single resistance form, the parallel resistance value of the load terminal must be close to or equal to the characteristic impedance of the transmission line; for the dual resistance form, each parallel resistance value It is twice the characteristic impedance of the transmission line.
The advantage of parallel termination matching is simple and easy. The obvious disadvantage is that it will bring DC power consumption: the DC power consumption of the single-resistance mode is closely related to the duty cycle of the signal; the dual-resistance mode is whether the signal is high or low. There is DC power consumption, but the current is less than half of the single resistor.
Common applications: more applications with high-speed signals.
(1) SSTL drivers such as DDR and DDR2. Use a single resistor form that is connected in parallel to VTT (typically half of IOVDD). The parallel matching resistor of the DDR2 data signal is built in the chip.
(2) High-speed serial data interfaces such as TMDS. In single-resistance form, parallel to IOVDD at the receiving device side, the single-ended impedance is 50 ohms (100 ohms between differential pairs).