Key factors for PCB EMC design
In addition to component selection and circuit design, good printed circuit board (PCB) design is also a very important factor in electromagnetic compatibility. The key to PCB EMC design is to minimize the reflow area and allow the reflow path to flow in the direction of the design. The most common return current problems come from cracks in the reference plane, changing the reference plane layer, and the signal flowing through the connector. Jumping capacitors or decoupling capacitors may solve some problems, but the overall impedance of the capacitors, vias, pads, and wiring must be considered. This lecture will introduce EMC's PCB design technology from three aspects: PCB layering strategy, layout skills and routing rules.
PCB layering strategy
The thickness of the circuit board design, the via process and the number of layers of the circuit board are not the key to solving the problem. Good layered stacking is to ensure the bypass and decoupling of the power bus and minimize the transient voltage on the power layer or the ground layer. And the key to shield the electromagnetic field of the signal and power supply. From the perspective of signal traces, a good layering strategy should be to put all signal traces on one or more layers, which are next to the power layer or ground layer. For the power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the "layering" strategy. In the following, we will talk about the excellent PCB layering strategy.
1. The projection plane of the wiring layer should be in the area of its reflow plane layer. If the wiring layer is not in the projection area of its reflow plane layer, there will be signal lines outside the projection area during wiring, causing "edge radiation" problems, and also causing the signal loop area to increase, resulting in increased differential mode radiation .
2. Try to avoid setting adjacent to the wiring layer. Because parallel signal traces on adjacent wiring layers can cause signal crosstalk, if the adjacent wiring layers cannot be avoided, the layer spacing between the two wiring layers should be properly increased to reduce the layer spacing between the wiring layer and its signal loop.
3. Adjacent plane layers should avoid overlapping their projection planes. Because when the projections overlap, the coupling capacitance between the layers will cause the noise between the layers to couple with each other.