Some preparations before PCB layout

1. Check if the capture point setting is correct. The 08 process is 0.1, the 06 process is 0.05, and the 05 process is 0.025.

2. The Cell name cannot begin with a digit. Otherwise, the DRACULA check cannot be done.

3. Consider the direction and location of the PIN before layout.

4. Pre-layout analysis circuit, complete the same function MOS tube drawn together

5. Pre-order the two layers of metal. The orientation of the grid in a figure is as uniform as possible, and there should be no horizontal and vertical.

Error check:

1. Is there a connection at each end of the DEVICE; the connection is correct;

2. When completing the layout check, check whether there is a connection in each wiring. Pay special attention to VSSX, VDDX.

3. Use the SHOTS to highlight the line when checking the line, so that you can find the metal lines that can be combined or shortened.

4. Multiple resistors (greater than two) are marked with DUMMY. Ensure that each resistor is in the same environment as the lithography. The outermost resistor has an NPIM layer that exceeds EPOLY2 by 0.55 um, which is half the pitch of the two resistors.

5. Unrelated MOS tube THIN should be disconnected, do not connect together

6. Parallel pipes pay attention to the leakage source merge, do not connect the wrong line. The source end of one tube is the drain end of another tube

7. The name of the uppermost pin when doing DRAC check is identified by text2. The name of Text2 should be the same as the name of the pin.

8. Do not do DIVA check on big CELL, use DRACULE.

9. Eliminate the lvs error of the resistor dummy, move the nimp and RPdummy layers to the edge of the resistor, do not cover the dummy

Way to save area

1. The device can be drawn under the power line. Save area.

2. The resistor can be routed above, and the area where the resistor is drawn can be fully utilized.

3. The longer the length of the resistor is drawn, the more the area is saved.

4. When the wire is routed, the width of the wire is minimized to save the area. The width of the hole is not required.

5. When making a new version of the layout diagram, the old map is saved, do not change or delete. If the line of the lower layer CELL is connected to the outer layer CELL when reducing the area, you can start from changing the connection and reduce the area of the line.

6. The area in the layout is divided by the interval of the device, device and the space of the trace. Reduce the area generally starting from the wiring space, change FLOORPLAN