The importance of PCB power integrity

In the PCB circuit design, generally we are concerned about the quality of the signal, but sometimes we often confined to the signal line to study, and the power and ground as an ideal situation to handle, although this can simplify the problem, but at high speed In design, this simplification is no longer practical. Although the direct result of circuit design is manifested in terms of signal integrity, we must not overlook the power integrity design. Because power integrity directly affects the signal integrity of the final PCB board. Both power integrity and signal integrity are closely related, and in many cases, the main cause of signal distortion is the power system. For example, ground bounce noise is too large, decoupling capacitors are not designed properly, loop effects are severe, multiple power/ground planes are not well segmented, ground design is unreasonable, current is not uniform, and so on.

1) PCB power distribution system

Power integrity design is a very complicated matter, but how to control the impedance between the power system (power supply and ground plane) is the key to design in recent years. Theoretically speaking, the lower the impedance between the power supply systems, the lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In actual design, we can determine the target impedance we want to reach by specifying the maximum voltage and power variation range. Then, we can make the impedance of the various parts of the power system (related to frequency) approach the target impedance by adjusting the relevant factors in the circuit.

2) Earthquake rebound

When the edge speed of a high-speed device is lower than 0.5 ns, the data exchange rate from the large-capacity data bus is particularly fast, and when it generates strong ripples in the power layer that are sufficient to affect the signal, power instability occurs. When the current through the ground loop changes, a voltage is generated by the loop inductance. When the rising edge is shortened, the current change rate increases, and the ground bounce voltage increases. At this point, the ground plane (ground) is not ideally zero level, and the power supply is not an ideal DC potential. As the gates for simultaneous switching increase, the ground bounce becomes more severe. For a 128-bit bus, there may be 50-100 I/O lines switching at the same clock edge. At this time, the inductance of the power supply and the ground loop fed back to the simultaneously switched I/O driver must be as low as possible, otherwise, a voltage brush will appear when the ground is connected to the same ground. Ground bounce can be seen everywhere, such as ground bounce on chips, packages, connectors, or circuit boards, which can lead to power integrity issues.

From the perspective of technology development, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to maintain a bounce-back is to reduce the power and ground distribution inductance. For chips, it means moving to an array wafer, placing power and ground as much as possible, and connecting to the package as short as possible to reduce inductance. For the package, it means moving the package to make the ground plane of the power supply more closely spaced, as used in the BGA package. For connectors, it means using more ground pins or redesigning connectors to have internal power and ground planes, such as connector-based ribbon cords. For a circuit board, it means that the adjacent power supply and the ground plane are as close as possible. Since the inductance is proportional to the length, connecting the power supply to ground as short as possible will reduce ground noise.

3) Decoupling capacitors

We all know that adding some capacitance between the power supply PCB and ground can reduce the noise of the system, but how much capacitance is added to the circuit board? How large is the capacitance of each capacitor? Where is each capacitor placed better? Similar to these Problems We generally do not seriously consider, but rely on the designer's experience to perform, and sometimes even think that the smaller the capacitance, the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors and the capacitance of each capacitor and the specific location to ensure that the system impedance is within the control range. A basic principle Decoupling capacitors are needed, one cannot be less, excess capacitance, one is not required.