The Via Design Principles of High-Speed PCBs
Through the analysis of the parasitic characteristics of vias, we can see that the developers of logistics software have introduced that in the high-speed PCB design, seemingly simple vias will often bring great negative effects to the circuit design. In order to reduce the adverse effects of the parasitic effects of via hole, you can do as much as possible in the design as below:
1. Considering the cost and signal quality, to choose a reasonably sized for via process . For example, for a 6-10 layers memory module PCB design, using 10/20 Mil (drill/pad) via are preferred. For some high density with small size boards, 8/18 Mil also can be used. Under current technical conditions, it is difficult to use smaller size via. For power or ground vias, If we use larger sizes via,it can reduce the impedance.
2. The two formulae be discussed above can be concluded that the use of a thinner PCB board can reduce parasitic parameter of two types via.
3. The signal circuit layout on the PCB should not be changed the layer if it can. It mean that it doesn’t need to use via if it is unnecessary.
4. The pins of the power supply and ground should be drilled in the nearest hole. The shorter the lead between the via and the pin, the better, because they will Causes an increase in inductance. At the same time, the leads of the power supply and ground should be as thick as possible to reduce the impedance.
5. Place some grounded via near the signal layer via to provide the closest circuit for the signal. You can even place a lot of extra ground via on the PCB board. Of course, you need to be flexible when you are designing. The previously discussed via model is a case where each layer has pads, and sometimes we can reduce or even remove pads from some layers. Especially in the case of high via density, it may lead to the formation of a broken channel in the copper layer, solving this problem. In addition to moving the location of the via, we can also consider to reduce pad size in the via in the copper layer.