High-speed FPC Design Process
By analyzing the parasitic characteristics of via hole, we can see that in high-speed PCB FPC design, seemingly simple via hole often have a large negative effect on the design of the circuit. In order to reduce the adverse effects of the parasitic effects of via hole, it is possible to do as much as possible in the design:
1.Consider the cost and signal quality, and choose a reasonable size of the via size. For example, for 6-10 layer memory module PCB design, 10/20Mil (drill/pad) via hole are better. For some high-density small-size boards, you can also try 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller size via hole. For via hole for power or ground, consider using larger sizes to reduce impedance.
2.The two formulas discussed above can be drawn, the use of a thin PCB board is beneficial to reduce the two parasitic parameters of the via.
3.The signal traces on the PCB should not be changed as much as possible, that is, try not to use unnecessary holes.
4.The power and ground pins should be drilled near the hole. The shorter the lead between the via and the pin, the better, because they will lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance.
5.Place some grounded via hole near the via hole of the signal-changing layer to provide the most recent loop for the signal. It is even possible to place a large number of redundant ground via hole on the PCB. Of course, you need to be flexible in design. The via model discussed above is where each layer has pads, and sometimes we can reduce or even remove pads from certain layers.
Especially in the case of very large via density, it may cause a broken channel in the copper layer to form a partition circuit. To solve such a problem, in addition to moving the position of the via, we can also consider the via in the copper layer. The pad size is reduced.