Via Design Principles In High-Speed PCBs
Through the analysis of the parasitic characteristics of vias, we can see that seemingly simple vias in high-speed PCB designs can also bring great negative effects to circuit design. In order to reduce the adverse effects of the parasitic effects of vias, you can do as much as possible in the design:
1. Considering the cost and signal quality, choose a reasonably sized via size. For example, for a 6-10 layer memory module PCB design, 10/20 Mil (drill/pad) vias are preferred. For some high density, small size boards, 8/18 Mil can be used. hole. Under current technical conditions, it is difficult to use smaller size vias. For power or ground vias, larger sizes can be considered to reduce the impedance.
2, the two formulas discussed above can be drawn, the use of a thin PCB board is conducive to reducing the two types of vias Health parameters.
3. The signal traces on the PCB should not be changed as much as possible, that is, try not to use unnecessary vias.
4, the power and ground pins should be near the hole, the shorter the lead between the via and the pin, the better, because they will lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance.
5. Place some grounded vias near the vias of the signal-changing layer to make the signal the nearest circuit. You can even place a lot of extra ground vias on the PCB board. Of course, you need to be flexible in design. The via model discussed above is where each layer has pads, and sometimes we can reduce or even remove pads from certain layers. Especially in the case of very high via density, it may cause a broken channel in the copper layer to form a partition circuit. To solve such a problem, in addition to moving the position of the via, we can also consider the via in the copper layer. The pad size is reduced.